JPH0810950Y2 - 電力半導体装置 - Google Patents

電力半導体装置

Info

Publication number
JPH0810950Y2
JPH0810950Y2 JP9716990U JP9716990U JPH0810950Y2 JP H0810950 Y2 JPH0810950 Y2 JP H0810950Y2 JP 9716990 U JP9716990 U JP 9716990U JP 9716990 U JP9716990 U JP 9716990U JP H0810950 Y2 JPH0810950 Y2 JP H0810950Y2
Authority
JP
Japan
Prior art keywords
power semiconductor
external connection
semiconductor device
end side
substrates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9716990U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0455151U (en]
Inventor
友広 鈴木
達也 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP9716990U priority Critical patent/JPH0810950Y2/ja
Publication of JPH0455151U publication Critical patent/JPH0455151U/ja
Application granted granted Critical
Publication of JPH0810950Y2 publication Critical patent/JPH0810950Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Combinations Of Printed Boards (AREA)
JP9716990U 1990-09-14 1990-09-14 電力半導体装置 Expired - Fee Related JPH0810950Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9716990U JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9716990U JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Publications (2)

Publication Number Publication Date
JPH0455151U JPH0455151U (en]) 1992-05-12
JPH0810950Y2 true JPH0810950Y2 (ja) 1996-03-29

Family

ID=31837300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9716990U Expired - Fee Related JPH0810950Y2 (ja) 1990-09-14 1990-09-14 電力半導体装置

Country Status (1)

Country Link
JP (1) JPH0810950Y2 (en])

Also Published As

Publication number Publication date
JPH0455151U (en]) 1992-05-12

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees